Circuit arrangement for generating a clock-pulse signal having a frequency synchronous with a reference clock-pulse signal

ABSTRACT

To synchronize a controllable oscillator with a first reference clock signal, a first phase locked loop having a first phase comparison device is provided. In addition, the synchronous-frequency clock signal from the oscillator is supplied to a second phase comparison device for phase comparison with a second reference clock signal via an inventive phase control element for inserting and removing clock phases. On the basis of the output signal from the second phase comparison device, phase correction information is formed and on the basis of this phase correction information the insertion and removal of clock phases is controlled in the phase control element. If the first reference clock signal disappears, the oscillator is stabilized using the second reference clock signal by taking into account the phase correction information formed previously.

CLAIM FOR PRIORITY

This application claims priority to International Application No.PCT/DE00/03219 which was published in the German language on Sept. 15,2000.

TECHINCAL FIELD OF INVENTION

The invention relates to a circuit having a clock signal with afrequency synchronous with a reference clock signal.

BACKGROUND OF THE INVENTION

In digital communications systems, individual communications systemcomponents require an accurate system clock for synchronizinginterchange of communications data. Normally, highly accurate referenceclock signals are supplied to individual communications systemcomponents for this purpose, e.g. via the public network. Generally, thereference clock signals supplied do not directly provide clock controlfor a communications system component, but rather are routed to a phaselocked loop in which system clock signals are formed and transmitted toindividual assemblies.

Since interference-free transmission of an external reference clocksignal cannot be guaranteed at all times, a communications systemcomponent is often provided with a dedicated highly stable referenceclock source which, in the event of the external reference clock signaldisappearing, is used to stabilize the clock generator via a secondphase locked loop.

Such a circuit arrangement is known from European patent application 0262 481, for example. This circuit arrangement contains a referencereception part which receives the external reference clock signals andis connected to a first input of a first phase comparison device. Theoutput of the first phase comparison device is routed via an integrationdevice and a filter whose output can be connected to a downstreamvoltage controlled oscillator using a switching element. Thesynchronous-frequency clock signals formed in the voltage controlledoscillator are routed from the latter's output both to an output of thecircuit arrangement and to a second input of the first phase comparisondevice.

The known circuit arrangement also contains a highly stable referenceclock source whose output is connected to a first input of a secondphase comparison device. The second input of this second phasecomparison device is likewise connected to the output of the voltagecontrolled oscillator. The output of the second phase comparison devicecan be connected either to an additional filter or to a minuend input ofa subtraction element using a further switching element. The output ofthe subtraction element, to whose subtrahend input the output of theadditional filter is connected, is connected to another input of theswitching element via a further filter.

The known circuit arrangement thus contains two phase locked loops, thefirst phase locked loop being controlled by the external reference clocksignals, and the second phase locked loop being controlled by thereference clock signals from the highly stable reference clock source.Normally, the voltage controlled oscillator is synchronized with thesupplied external reference clock signals. If the external referenceclock signals disappear or if prescribed phase differences are exceeded,there is a switch to the highly stable reference clock source. In theadditional filter, during synchronization by the external referenceclock signals, the discrepancies between the synchronous-frequency clocksignals and the reference clock signals from the highly stable referenceclock source are gathered and correction adjustment information isformed. After switching to the highly stable reference clock source, thesubtraction element is used to include this correction adjustmentinformation in the formation of adjustment information for the voltagecontrolled oscillator.

However, this circuit arrangement has the problem that, to avoid anexcessively long regulation delay, the frequency of the highly stablereference clock source should be comparatively high. A high clockfrequency also results in a comparatively high current consumption,however, which means that such a circuit arrangement is not verysuitable for battery operation. In addition, such a circuit arrangementis provided with switching means in order to detect cyclically occurringphase overflows in the second phase comparison device. In this context,phase overflow denotes when a phase difference of 360 degrees isexceeded. Such phase overflows occur cyclically if the frequency of thereference clock source and the frequency of the voltage controlledoscillator, synchronized with the external reference clock signal,differ from one another systematically, possibly after they have eachpassed through a frequency divider.

SUMMARY OF THE INVENTION

In one embodiment of the invention, there is a circuit arrangement forproducing a clock signal whose frequency is synchronous with that ofreference clock signals which has an improved regulation characteristic,in particular when a reference clock signal having a comparatively lowclock frequency is supplied.

The circuit arrangement includes, for example, an oscillator whose clockfrequency, in a first operating mode of the circuit arrangement,synchronized with a supplied, first reference clock signal using a firstphase locked loop which comprises a first phase comparison device. Inaddition, a phase control element and a second phase comparison deviceare provided which are used in the first operating mode to detect adiscrepancy between a supplied, second reference clock signal and thesynchronous-frequency clock signal from the oscillator and to form phasecorrection information. In a second operating mode of the circuitarrangement, e.g. if the first reference clock signal disappears, theoscillator is no longer synchronized using the first reference clocksignal, but rather using the second reference clock signal. Such asecond operating mode is often also referred to as “hold-over mode”. Inthis case, the phase correction information formed in the firstoperating mode is brought into the phase control. This is done by virtueof a phase control element inserting or removing clock phases in theclock signal from the oscillator on the basis of the phase correctioninformation before phase comparison with the second reference clocksignal.

Correction of the oscillator phase or oscillator frequency before phasecomparison with the second reference clock signal makes it easy toprevent cyclically occurring phase overflows during phase comparisonwhen there is a systematic discrepancy between the oscillator clocksignal, whose frequency is synchronous with that of the first referenceclock signal, and the second reference clock signal.

One advantage of the circuit arrangement provides very good regulationcharacteristic and short regulation time constants which are ensured, inparticular, even for a comparatively low-frequency second referenceclock signal. The production of low-frequency reference clock signalsgenerally requires less power than the production of higher-frequencyreference clock signals, which means that the circuit arrangement inconjunction with a low-frequency reference clock generator is also wellsuited to battery operation. The good regulation characteristic is aconsequence of the phase correction by the phase control element beingapplied to the clock signal from the oscillator. Since the clock signalfrom the oscillator normally has a much higher frequency than the secondreference clock signal, removal or insertion of individual clock phasesin the clock signal from the oscillator makes it possible to control thefrequency of this clock signal very precisely before phase comparison.In particular, this causes only very low phase and pulse jitter.

Another advantage of the inventive circuit arrangement is that noprocessor is required for implementing it. Instead, the circuitarrangement can be implemented using an inexpensive ASIC chip(Application Specific Integrated Circuit), for example.

In one aspct of the invention, the output of the first phase comparisondevice can be connected to the frequency control input of the oscillatorvia a switching element, such as a transistor, a logic gate or amultiplex device. This switching element can be actuated such that it ison in the first operating mode of the circuit arrangement and is off inthe second operating mode.

Connected upstream of the frequency control input of the oscillatorthere may also be a filter, such as a simple low-pass filter or a “P, PIor PID filter”, for integrating frequency control signals supplied tothe oscillator. The frequency control input of the oscillator may oftenalso perform such a filter function itself.

In addition, a memory can be provided which keeps the phase correctioninformation formed in the first operating mode stored in it for as longas the circuit arrangement is in the second operating mode. In thesecond operating mode, the insertion and removal of clock phases is thencontrolled in the phase control element on the basis of the stored phasecorrection information.

To be able to compare two different clock signals using a phasecomparison device, it is generally necessary for the clock signals whichare to be compared to have the same nominal frequency. To compare clocksignals having different nominal frequencies, these clock signals canrespectively be supplied to the phase comparison device via a frequencydivider. In this case, the division factor of a respective frequencydivider is proportioned such that the divided nominal frequenciesapplied to the inputs of the phase comparison device are the same.

In accordance with one advantageous embodiment of the invention, adetector device can be provided which can be used to identify whetherthe first reference clock signal is present. An output of the detectordevice can be connected to one or more switching elements forcontrolling and/or changing over the operating mode.

In accordance with another advantageous embodiment of the invention, theregulating device can have an up/down counter whose counting directionis dependent on the output signal from the second phase comparisondevice. The up/down counter can be actuated, by way of example, suchthat its counter reading is either incremented or decremented atprescribed times, e.g. in each case on the positive or negative edges ofthe second reference clock signal, depending on whether the phasedifference established is positive or negative. If the phases are equal,the counter reading can remain the same.

In addition, a phase control element controller having a countingregister can be provided, the counting register being able to be loadedwith the counter reading from the up/down counter as a counting preset.In this context, the counting register can be advanced starting from thecounting preset, for example with timing prescribed by a clock signal,in order to prompt insertion or removal of a clock phase in the phasecontrol element when a prescribed counting marker is reached.

In addition, the counting register can be split into a first registerpart for more significant bits and a second register part for lesssignificant bits, with a counting frequency used to advance the secondregister part being determined by the content of the first registerpart. This functional isolation of the register parts allows a very widecontrol range to be achieved even when the length of the countingregister or of the up/down counter is short. In this context, regulationis more accurate the lower the value of the more significant bits of thecounting preset which determine the counting frequency, i.e. the lessthe clock signals which are to be compared by the second phasecomparison device differ from one another.

In accordance with another advantageous embodiment of the invention,another phase control element, controlled by the regulating device, forderiving a further synchronous-frequency clock signal from the secondreference clock signal can be provided. This allows asynchronous-frequency clock signal to be provided for a meterapplication, for example.

BRIEF DESCRIPTION OF THE DRAWINGS

An exemplary embodiment of the invention is explained in more detailbelow with reference to the drawings, in which

FIG. 1 shows a schematic illustration of an inventive circuitarrangement.

FIG. 2 shows a graphical illustration of phase relationships for clocksignals.

DETAILED DESCRIPTION OF THE PREFFERED EMBODIMENT

FIG. 1 shows a schematic illustration of a circuit arrangement forproducing a clock signal T0 whose frequency is synchronous with that ofthe supplied reference clock signals RT1 and RT2. The circuitarrangement has a first phase locked loop which comprises a first phasecomparison device PV1, a filter F and a voltage controlled oscillator, aso-called VCXO (Voltage Controlled X-tal Oscillator). In a firstoperating mode of the circuit arrangement, the output of the phasecomparison device PV1 is connected to a filter F via a switching elementS2 and, via said filter F, to a frequency control input of theoscillator VCXO, which forms the clock signal T0 to be synchronized. Thefilter F is used for integrating frequency control signals supplied tothe oscillator VCXO and, by way of example, can be in the form of alow-pass filter or a “P, PI or PID filter”.

In the first operating mode, the clock signal T0 is synchronized withthe first reference clock signal RT1. For the purposes of synchronizingcommunications devices, such a first reference clock signal RT1 is oftenderived from network clock signals, from signals transmitted by thepublic communications network or from signals received wirelessly from atime information transmitter. The first reference clock signal RT1 issupplied to a first input E1 of the first phase comparison device PVlvia a frequency divider T1. Likewise, the clock signal T0 from theoscillator VCXO is supplied to a second input E2 of the first phasecomparison device PVl via a frequency divider T2. In this case, thedivision factors of the frequency dividers T1 and T2 are proportionedsuch that the respectively divided nominal frequencies of the clocksignal T0 and of the first reference clock signal RT1 are the same ineach case.

Additional components in the circuit arrangement may include, forexample, a phase control element PS for inserting and removing clockphases in the clock signal T0, a second phase comparison device PV2 anda regulating device RE. In the first operating mode of the circuitarrangement, the components are used to record any discrepancy betweenthe clock signal T0 whose frequency is synchronous with that of thefirst reference clock signal RT1 and the second reference clock signalRT2. To this end, the second reference clock signal RT2 is supplied to afirst input El of the second phase comparison device PV2. In this case,the second reference clock signal RT2 can be produced, by way ofexample, by a temperature compensated oscillator, a so-called tcxo(Temperature Compensated X-tal Oscillator). For the present exemplaryembodiment, it may be assumed that the second reference clock signal RT2has a typical application frequency of 32 768 Hz. The use of such acomparatively low frequency has the advantage that the second referenceclock signal RT2 can be produced using commercially available tcxoswhich have a current consumption of a few microamps. This means that theinventive circuit arrangement in conjunction with a comparativelylow-frequency TCXO as the second reference clock source is also wellsuited to battery operation.

For the purposes of phase comparison with the second reference clocksignal RT2, the clock signal T0 from the oscillator VCXO is supplied toa second input E2 of the second phase comparison device PV2 via thephase control element PS and a frequency divider T3 in order to matchthe oscillator's nominal frequency to the frequency of the referenceclock signal RT2. At a typical oscillator nominal frequency of 16 384MHz, for example, a frequency divider T3 having a division factor of 500needs to be provided for the purposes of matching to the frequency of 32768 Hz of the second reference clock signal RT2. Such a high oscillatorfrequency allows particularly precise regulation as a result of theinsertion and removal of clock phases.

In the first operating mode, the output signal from the second phasecomparison device PV2 is supplied to an up/down counter UDC in theregulating device RE via a switching element S1 and determines thecounting direction of said counter. The counting frequency of theup/down counter UDC is prescribed by the second reference clock signalRT2, which is likewise supplied to said counter. By way of example, theup/down counter UDC can be incremented whenever a phase edge of thesecond reference clock signal RT2 leads the corresponding phase edge ofthe divided clock signal T0, and can be decremented accordingly wheneverit lags. The up/down counter UDC is stopped if the phases areapproximately equal. In this context, phases can be regarded as beingapproximately equal if the respective phase difference measured iswithin a prescribed interval. A respective counter reading ZS on theup/down counter UDC represents accumulated phase correction informationwhich describes a discrepancy between the clock signal T0 whosefrequency is synchronized with that of the first reference clock signalRT1 and the second reference clock signal RT2, and hence describes thediscrepancy between the first and second reference clock signals.

In addition, the regulating device RE comprises a phase control elementcontroller PSS having a counting register which is split into a firstregister part LOG for more significant bits and a second register partLIN for less significant bits. The phase control element controller PSSalso contains a frequency divider T4 to which the clock signal T0 fromthe oscillator VCXO is supplied before it passes through the phasecontrol element PS. The division factor TF of the frequency divider T4is determined by the content of the register part LOG of the countingregister. The divided output frequency of the frequency divider T4 canthus be varied within wide limits, e.g. typically between 4 Hz and 4096Hz. The clock signal T0 divided by the frequency divider T4 prescribes acounting clock signal ZT which is used to advance the register part LINof the counting register.

To control the phase control element PS, the counter reading ZS on theup/down counter UDC is transferred as a counting preset to the countingregister in the phase control element controller PSS. The moresignificant bits of the counter reading ZS which are transferred to theregister part LOG thus stipulate a division factor TF for the presentinstant, while the less significant bits of the counter reading ZS whichare transferred to the register part LIN prescribe a new start value forcounting. After the counter reading ZS has been transferred, theregister part LIN is advanced with the timing of the counting clocksignal ZT up to a prescribed counting marker. When this counting markeris reached, the phase control element controller PSS forms a controlsignal SS which is supplied to the phase control element PS and at thatpoint prompts removal or insertion of a clock phase in the clock signalT0 from the oscillator VCXO. On the basis of an arithmetic sign bit forthe counter reading ZS, a decision is then made regarding whether acontrol signal for insertion or a control signal for removal of a clockphase is formed. In addition, when the prescribed counting marker isreached, the content of the counting register is renewed by subsequentlyloading a counter reading ZS for the present instant from the up/downcounter UDC, and hence a renewed counting pass in the counting registeris initiated.

In a second operating mode of the inventive circuit arrangement, towhich mode there can automatically be a switch if the first referenceclock signal RT1 disappears, for example, the clock signal T0 issynchronized using the second reference clock signal RT2, including thephase correction information ZS formed in the first operating mode. Inthis context, the synchronism with the first reference clock signal RT1,which is no longer used, should be maintained as accurately as possible.

A switch to the second operating mode is effected by changing over theswitching elements S1 and S2. To this end, the switching element S1 isused to isolate the output of the second phase comparison device PV2from the up/down counter UDC and instead to connect it to an input ofthe switching element S2 via a connection indicated by a dotted line.This input is coupled to the frequency control input of the oscillatorVCXO via the filter F by changing over the switching element S2.Changing over the switching element S2 interrupts the previousconnection between the output of the phase comparison device PV1 and thefilter F. Changing over the switching elements S1 and S2 as describedforms a second phase locked loop comprising the oscillator VCXO, thephase control element PS, the second phase comparison device PV2 and thefilter F. The clock signal T0 is thus synchronized using the secondreference clock signal RT2.

When the second phase comparison device PV2 has been isolated from theup/down counter UDC, the counter is stopped. In this case, its lastcounter reading ZS continues to be stored as phase correctioninformation and is used, as in the first operating mode, for subsequentloading of the counting register in the phase control element controllerPSS. The insertion and removal of clock phases is continued by the phasecontrol element controller PSS. That is, as stipulated by the lastcounter reading ZS on the up/down counter UDC, which is constant in thesecond operating mode. This means that the phase control in the secondphase locked loop is corrected by the last discrepancy establishedbetween the second reference clock signal RT2 and the first referenceclock signal RT1, so that, with a high degree of accuracy, the clocksignal T0 remains synchronous with the first reference clock signal RT1,which is no longer present.

FIG. 2 illustrates the change in the time profile of the clock signal T0as a result of removal and insertion of clock phases by the phasecontrol element. While the top curve shows the time profile for a clocksignal which has not been changed by the phase control element PS, themiddle curve shows a clock signal with a clock phase removed and thebottom curve shows a clock signal with a clock phase inserted.

In the present exemplary embodiment, the phase control element PS isproduced in a particularly simple manner using a 2-bit counter. Thecounter runs through the counting steps 0,1,2 and 3 during one clockperiod of the clock signal T0. The output signal from the phase controlelement PS is derived from the state of the more significant bit of the2-bit counter, i.e. the output signal is at zero during the countingsteps 0 and 1 and is at one during the counting steps 2 and 3. Therespective counting steps of the counter are indicated below theillustrated clock signal curves in each case.

A clock phase is now removed by skipping one counting step of the 2-bitcounter when prompted by the control signal SS. This means that thephase of the subsequent clock pulses jumps forward by 90°. Similarly, aclock phase is inserted by suppressing a counting pulse which wouldotherwise cause the 2-bit counter to be advanced, the result of thesuppression being that the 2-bit counter is not advanced again until thenext counting pulse. This shifts the phase of subsequent clock pulsesbackward through 90°.

What is claimed is:
 1. A circuit arrangement for producing a clocksignal having a frequency synchronous with reference clock signals,comprising: an oscillator providing the synchronous-frequency clocksignal and having a clock frequency controllable via a frequency controlinput; a first phase comparison device having a first input to couple afirst reference clock signal, a second input, to which the clock signalfrom the oscillator is supplied, and an output which is routed to thefrequency control input of the oscillator; a second phase comparisondevice having a first input to couple a second reference clock signaland an output configured for coupling to the frequency control input ofthe oscillator via a switching element on the basis of operating mode; aphase control element to insert and remove clock phases used to supplythe clock signal from the oscillator to a second input of the secondphase comparison device, with insertion and removal of clock phasescontrollable via a control input of the phase control element; and aregulating device configured for connection to the output of the secondphase comparison device via a switching element on the basis ofoperating mode to form phase correction information on the basis of thesecond phase comparison device's output signal and which is connected tothe control input of the phase control element to control insertion andremoval of clock phases on the basis of the phase correctioninformation.
 2. The circuit arrangement as claimed in claim 1, whereinthe output of the first phase comparison device is routed to thefrequency control input of the oscillator via a switching elementconfigured for connecting and isolating the output of the first phasecomparison device and the frequency control input of the oscillator onthe basis of operating mode.
 3. The circuit arrangement as claimed inclaim 1, further comprising: a filter connected upstream of thefrequency control input of the oscillator to integrate frequency controlsignals supplied to the oscillator.
 4. The circuit arrangement asclaimed in claim 1, further comprising: a memory to store the phasecorrection information on the basis of operating mode.
 5. The circuitarrangement as claimed in claim 1, wherein, a frequency divider isconnected upstream of at least one input of at least one phasecomparison device.
 6. The circuit arrangement as claimed claim 1,wherein, an output of a detector device which indicates when the firstreference clock signal is present is connected to a switching element tocontrol the operating mode.
 7. The circuit arrangement as claimed inclaim 1, wherein an output of a detector device which indicates when thesecond reference clock signal is present is connected to an alarmtransmitter to trigger an alarm signal when the second reference clocksignal is not present.
 8. The circuit arrangement as claimed in claim 1,wherein an output of a detector device which indicates when the clocksignal from the oscillator is present is connected to an alarmtransmitter to trigger an alarm signal when the clock signal is notpresent.
 9. The circuit arrangement as claimed in claim 1, wherein, theregulating device has an up/down counter whose counting direction isdependent on the output signal from the second phase comparison deviceand whose counter reading represents the phase correction information.10. The circuit arrangement as claimed in claim 9, wherein theregulating device has a phase control element controller having acounting register configured to load the counter reading from theup/down counter as a counting preset and prompts insertion or removal ofa clock phase in the phase control element when a prescribed countingmarker is reached.
 11. The circuit arrangement as claimed in claim 10,wherein the counting register is split into a first register part formore significant bits and a second register part for less significantbits, and a counting frequency used to count through the second registerpart is determined by the content of the first register part.
 12. Thecircuit arrangement as claimed in claim 1, further comprising: anotherphase control element, controlled by the regulating device, to deriveanother synchronous-frequency clock signal from the second referenceclock signal.